Important Concepts of Physical Design

In our day2day life delay is a word used to describe something which is late or which is completed after the scheduled time. 

In VLSI delay simply means the time taken by the signal to travel or propagate from one point to another. 



The diagram shows a part of the logic. It contains 3 cells namely cell1 ,cell 2 and cell3 connected by nets net1 and net2.

Cell1 has input and output pins called i1 and o1 respectively. Similarly the pins for cell2 and cell3 are i2, o2, i3 and o3.

Cell Delay : 

In cell1 the time the signal takes from i1 to o1 is internal to the cell and is known as the cell delay.

Net Delay :

The time taken by the signal to propagate from the output of cell1 which is o1 to the input of cell2 which is i2, is called the net delay. Notice here that the signal travels through net1.


Network Delay :

If we consider the above diagram as a small network then, the time taken by the signal i1 (the input of cell1) to o3 (the output of cell3) is called the network delay.

Source Delay :

Let us consider that the